The present invention relates to a semiconductor device having a non-volatile memory cell which can be electrically erased and written; and, more particularly, the invention relates to a non-volatile semiconductor storage device, such as a flash memory, in which a threshold voltage associated with multiple-valued information comprising four values or more can be programmed in one memory cell and to a method for changing a threshold of a non-volatile cell memory. For example, the invention relates to a technique which is effectively used in a data processing system, such as a file memory system utilizing such a nonvolatile semiconductor storage device.
Non-volatile semiconductor storage devices, e.g., flash memories, have been provided which can store imfor-mation through injection and extraction of electrons to and from a floating gate. A flash memory includes a memory cell transistor having a floating gate, a control gate, a source and a drain. The threshold voltage of such a memory cell transistor increases as electrons are injected into the floating gate and decreases as electrons are extracted from the floating gate. The memory cell transistor stores information that depends on whether the threshold voltage is higher or lower than a word line voltage (a voltage applied to the control gate) for data readout. In this specification, a state in which the threshold voltage is lower is referred to as an xe2x80x9cerase statexe2x80x9d and a state in which it higher is referred to as a xe2x80x9cwrite statexe2x80x9d, although this is not a limitation of the invention.
There are flash memories of this type in which information comprising four or more values is stored in one memory cell transistor. An example of articles that describe such multiple-valued memories appears on pages 48 and 49 of xe2x80x9cNikkei Microdevicexe2x80x9d (November, 1994 issue). Another example is Japanese Patent Laid-Open No. 297996/1997.
In a multiple-valued memory, for example, information comprising four values can be stored in one memory cell transistor by allowing selection of one state from among an erase state and first, second and third write states whose threshold voltages relative to that of the erase state are different from each other. When an erase operation precedes a write operation, information comprising four values can be stored by selecting none of the first, second and third write states or selecting any one of the write states. During a write operation for this purpose, write control information is necessary to determine whether to select a write operation to achieve one of the first, second or third write states. Such write control information can be maintained using a sense latch circuit and a data latch circuit provided for each bit line.
For example, the sense latch circuit comprises a static latch; one end of a bit line is connected to each of a pair of input and output terminals of the sense latch circuit; and the drain of the memory cell transistor is connected to each bit line. Further, the data latch circuit is connected to the other end of each bit line. The sense latch circuit senses whether a current flows or not between the source and drain of the memory cell transistor when a read voltage or a verify voltage is applied to the control gate of the same. Bit lines at the non-operation selection side of the sense-latch circuit are precharged at a reference level. When a high potential difference is formed between the control gate and the drain, it is possible to identify whether each memory cell is selected or not for writing by increasing or decreasing the drain voltage of the memory cell. In this case, the sense latch circuit latches data depending on the whether a write operation is selected or not. This latch data is the write control information described above.
Such write control information is generated by a data conversion circuit for every two bits of write data supplied externally and is latched in the sense latch circuits for bit lines selected to be written and the data latch circuits for each of the pairs of bit lines that share the sense latch circuit. When a write operation is performed on each word line, write control information is latched in advance in the sense latch circuits and data latch circuits for all bit lines that share the word line.
During a write operation, it is first determined whether the first write state is present or not according to write control information latched in a sense latch circuit. Next, it is determined whether the second write state is present or not according to write control information transferred internally from one of the data latch circuits to the sense latch circuit. Further, it is determined whether the third write state is present or not according to write control information transferred internally from the other data latch circuit to the sense latch circuit. Thus, four-valued information identified by two bits of data can be stored in one memory cell. During the write operation in the first, second and third write states described above, a verify operation is performed to check whether a threshold voltage assigned to each of the write states has been reached or not.
At this tine, some memory cells may be overwritten relative to the first, second or third write state, and, in an overwrite state, the threshold voltage may not be distinguished from other write states. For example, the threshold voltage of a memory cell which should be in the first write state can be increased to a level at which it can not be distinguished from the threshold voltage in the second write state. In such a case, the write operation is redone from the beginning by performing the write operation again after performing an erase operation on the memory cells which are to be written.
However, once a write operation is performed in the first, second or third write state, the write control information latched in the sense latch circuit is overwritten and erased by another piece of write control information transferred internally from a data latch circuit. Therefore, in order to perform a rewrite operation attributable to overwrite, the same write data must be received from the outside again. For this reason, a control circuit that controls access to a flash memory must maintain write data in a work memory or the like for a certain period of time after the write operation to the flash memory. The inventors have discovered that this increases the burdens associated with the control over access to a flash memory and can therefore reduce the efficiency of flash memory access or data processing.
The above-described situation similarly occurs in the case of additional writing. For example, a flash memory is used for a file memory system or the like which is compatible with a file system based on a magnetic disc storage device, such as a hard disc device. In this case, a part of the storage area of a flash memory is assigned to a management area which is separate from a user area. In a flash memory that accommodates write and erase on a word line basis, memory cells for one word line (hereinafter simply referred to as xe2x80x9csectorxe2x80x9d) are assigned to a user area and a management area, and the management area stores information on the validity of the user area of the associated sector and information on the number of rewrites. It may be required to perform the storage of such information separately from the rewrite of user data in a sector because of the nature of the information. Additional writing is a mode of a write operation that can meet such a requirement.
In the case of an additional write operation, additional write data is supplied to memory cells selected for writing. Since the write operation is performed sector by sector, it is necessary to save the data in memory cells which are unselected for writing, and both of the saved data and the additional write data must be written in the write operation.
However, the write operation must be redone from the beginning also in this case if an overwrite state or the like occurs. In doing so, if data for rewrite is to be supplied again externally, the control circuit controlling access to the flash memory must maintain the data for rewrite for a certain period of time after the additional write operation on the flash memory just as in the case of a write operation as described above. This increases the burdens associated with control over access to the flash memory and can reduce the efficiency of access to the flash memory or data processing.
The inventors also studied a write verify operation on a flash memory. During a write operation, the threshold voltage is gradually varied while repeating application of a high write voltage and verification. When it is determined that the threshold voltage of a memory cell has reached a target value in the course of such an operation, write voltage disabling information is latched in the sense latches of the bit lines connected to the memory cell, and, thereafter, the write voltage will never be applied to the memory cell once determined to have reached the write threshold voltage. At the initial stage of a write operation, however, since most memory cells have not reached a required write threshold voltage, a high current flows to the sources of the memory cells during write verification to increase the apparent threshold. Therefore, some of memory cells which have passed a verify operation at the initial stage of a write operation may not have reached a required write threshold voltage. In such a case, problems can arise in the configuration in which the write voltage can never be applied to the memory cells once determined to have reached the write threshold voltage.
The inventors have also studied an erase operation. As a result, it was found that it is important to make the distribution of the threshold voltages of memory cells in an erase state as uniform as possible when consideration is given to the efficiency of a write operation that follows an erase operation or the reliability of the written data.
It is an object of the invention to provide a semiconductor device in which it is possible to prevent additional write data supplied externally or data read out from memory cells to be saved from being lost each time an additional write operation is performed
It is another object of the invention to provide a semiconductor device which does not need to receive additional write data supplied from outside again to repeat an additional write operation.
It is still another object of the invention to provide a semiconductor device in which the reliability of a write verify operation can be improved by a verify operation which is performed even when a write verify operation has once resulted in a determination that an anticipated threshold voltage has been reached.
It is another object of the invention to provide a semiconductor device in which the distribution of threshold voltages of memory cells in an erase state can be made uniform.
It is another object of the invention to provide a method of changing a threshold of a non-volatile memory cell.
The above and other objects and novel features of the present invention will be apparent from the description provided in this specification and from the accompanying drawings.
Typical aspects of the invention disclosed in this specification can be briefly summarized as follows.
(1) According to a first aspect of the invention, there is provided a semiconductor device (1) to which additional write data are input (WS3) to perform an additional write operation through a process of logically synthesizing data read from memory cells and the additional write data (WS4), bulk erasure (WS5) and writes (RS1 through TS4) and a method for changing a threshold of the same. Memory cells of this semiconductor device may store either binary information or multi-valued information.
More specifically, the semiconductor device comprises bit lines (G-BLR and G-BLL) to which a plurality of electrically erasable and writable non-volatile memory cells (MC), a sense latch circuit (SL) and data latch circuits (DLR and DLL) are connected and control means (18) for latching information read from the non-volatile memory cells through the sense latch circuit in the data latch circuits and for controlling a write operation on the non-volatile memory cells based on data latched in the data latch circuits. The control means inputs additional write data in the data latch circuits. It performs a logical synthesis process based on the input additional write data and data read from the memory cells to obtain data for programming non-volatile memory cells in a write state into the same write state and for programming non-volatile memory cells in an erase state into a write state which is indicated by the additional write data. It latches the data obtained by the logical synthesis process in the data latch circuits and performs writing to the non-volatile memory cells in accordance with the latched data. Thus, the additional write operation can be performed with theologically synthesized data latched in the data latch circuits. Specifically, the logically synthesized data are latched in the data latch circuits; it is determined at each of a plurality of steps of a write operation to which of multi-valued threshold voltages the latched data correspond so as to latch write control information as a result of the determination in the sense latch circuit; and a write operation having multiple steps is performed to set the multi-valued threshold voltages in the memory cells in accordance with the write control information latched in the sense latch circuit.
Therefore, logically synthesized data will remain in the data latch circuits even after completion of the additional write operation. By maintaining the data of the result of the logical synthesis process in the data latch circuits until the write operation is completed, the latched data can be reused against abnormal writing to eliminate the need for receiving the write data again from the outside when the additional write operation is performed again. Therefore, a control circuit that controls access to the, semiconductor device is not required to hold write data in a work memory or the like for a certain period of title after a write operation on the semiconductor device. This makes it possible to improve the efficiency of memory access and data processing associated with memory access of the semiconductor device.
After the data obtained by the logical synthesis process are latched in the data latch circuits, a write operation on non-volatile memory cells in accordance with the data as a result of the logical synthesis process latched in the data latch circuits can be preceded by an erase operation (erase back or weak erase) performed on the non-volatile memory cells to be written. Thus, even in the case of additional writing, the memory cells are substantially put in an erase state immediately before the additional writing. This makes it possible to eliminate restrictions on the number of additional writes within the range of endurance to rewriting, thereby improving the reliability of additionally written data.
A semiconductor device in which, specifically, said means is specialized for storage of information having four or more values, comprises:
a sense latch circuit having a pair of input/output terminals;
a bit line provided in association with each of the input/output terminals of the sense latch circuit;
a plurality of electrically erasable and writable non-volatile memory cells connected to the bit line;
a plurality of data latch circuits connected to the bit line;
control means for latching information read from the non-volatile memory cells through the sense latch circuit in accordance with a threshold voltage state programmed in the non-volatile memory cells in the plurality of data latch circuits as multi-valued information having four or more values and for programming a threshold voltage state for writing in the non-volatile memory cells based on the multi-valued information latched in the plurality of data latch circuits. The control means inputs additional write data as multi-valued information in the data latch circuits, then performs a logical synthesis process based on the input additional write data and the multi-valued information read from the non-volatile memory cells to obtain multi-valued information for programming non-volatile memory cells having a threshold voltage state for writing into the same threshold voltage state for writing and for programming non-volatile memory cells having a threshold voltage state for erasure into a threshold voltage state for writing which is indicated by the additional write data, latches the multi-valued information obtained by the logical synthesis process in the data latch circuits and programs the threshold voltage state of the non-volatile memory cells in accordance with the latched multi-valued information.
[2] According to a second aspect of the inventions write verify operation is performed each time using data latched in the data latch circuits (DLR and DLL) which primitively latch write data whether the data are multi-valued or binary. Specifically, a semiconductor device comprises:
a bit line to which a plurality of electrically erasable and writable non-volatile memory cells are connected;
a sense latch circuit and a data latch circuit connected to the bit line; and
control means (18) for latching information read from the non-volatile memory cells through the sense latch circuit in the data latch circuit and for controlling a write operation on the nonvolatile memory cells sector by sector as a unit for writing based on the data latched in the data latch circuit. The control means applies a write voltage to non-volatile memory cells selected for writing in a sector to be written using the data latched in the data latch circuit at the time of a write operation (WS11) and determines whether the threshold voltage state has reached a target threshold voltage state as a result of the application of the write voltage using data latched in the data latch circuit at each process of applying the write voltage (WS12 and WS13).
According to this, the write verify operation is performed each time using data stored in the data latch circuit. As a result, even when a write verify operation provides an erroneous determination that a desired threshold voltage has been reached at the initial stage of writing or the like, the failure can be checked to allow rewriting.
The execution of an erratic/disturb detection operation after writing makes it possible to detect any abnormality in a threshold voltage distribution attributable to writing.
When multi-valued information is stored in the non-volatile memory cells, erratic/disturb detection first detects word disturbances that result in overwrite failures with high probability. This makes it possible to reduce the processing time spent before the detection of any failure.
[3] According to a third aspect of the invention write back is performed on memory cells in an over-erased state to prevent depletion after erasure whether the data is multi-valued or binary (selective writing is performed in memory cells whose threshold voltage is at a predetermined voltage or less) to keep memory cells in an erased state at threshold voltages equal to or higher than a predetermined voltage. Further, disturb detection is performed after the write back to prevent depletion to detect abnormal threshold voltages. These features make it possible to provide memory cells in an erase state with a uniform threshold voltage distribution.
An erase verify operation is performed prior to erasure to erase only sectors which fail the verification. This makes it possible to eliminate waste of time associated with an erase operation.
[4] For example, the semiconductor devices may be semiconductor memories formed on a single semiconductor substrate, such as flash memories or microcomputers, microprocessors and the like having an on-chip flash memory. The flash memory in the form of a semiconductor memory makes it possible to configure data processing systems such as non-volatile memory cards as PC (personal computer) cards. Such a data processing system includes, on a card substrate thereof, a semiconductor device in the form of a flash memory, access control means for controlling access to the semiconductor device and interface means for allowing the access control means to be interfaced to the outside of the system.